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LH5116S
FEATURES * 2,048 x 8 bit organization * Access time: 1000 ns (MAX.) * Low-power consumption: Operating: 33 mW (MAX.) Standby: 3.3 W (MAX.) * Fully-static operation * Three-state outputs * Single +3 V power supply * Package: 24-pin, 450-mil SOP DESCRIPTION
The LH5116S is a static RAM organized as 2,048 x 8 bits. It is fabricated using silicon-gate CMOS process technology. It operates at a low supply voltage of 3 V 10%.
CMOS 16K (2K x 8) Static RAM
PIN CONNECTIONS
24-PIN SOP A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 WE OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4
5116S-1
TOP VIEW
Figure 1. Pin Connections for SOP Package
1
LH5116S
CMOS 16K (2K x 8) Static RAM
ROW DECODERS
ROW ADDRESS BUFFERS
A0 8 A5 3 A6 2 A7 1 A8 23 A9 22 A10 19
MEMORY CELL ARRAY (128 x128)
24 VCC 12 GND
CE
DATA CONTROL
I/O1 9 I/O2 10 I/O3 11 I/O4 13 I/O5 14 I/O6 15 I/O7 16 I/O8 17
COLUMN I/O CIRCUITS
COLUMN DECODERS
COLUMN ADDRESS BUFFERS CE
CE 18 WE 21 OE 20 4 A4 5 A3 6 A2 7 A1
5116S-2
Figure 2. LH5116S Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A10 CE OE WE
Address input Chip Enable input Output Enable input Write Enable input
I/O1 - I/O8 VCC GND
Data input/output Power supply Ground
TRUTH TABLE
CE OE WE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE
L L H L
NOTE: 1. X = H or L
X L X H
L H X X
Write Read Deselect Output disable
DIN DOUT High-Z High-Z
Operating (ICC) Operating (ICC) Standby (ISB) Operating (ICC)
1 1 1
2
CMOS 16K (2K x 8) Static RAM
LH5116S
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN Topr Tstg
-0.3 to +7.0 -0.3 to VCC +0.3 0 to +50 -55 to +150
V V C C
1 1
NOTE: 1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +50C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage Input voltage
VCC VIH VIL
2.7 2.2 -0.3
3.0
3.3 VCC + 0.3 0.8
V V V
DC CHARACTERISTICS (VCC = 3 V 10%, TA = 0 to +50C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Output `LOW' voltage Output `HIGH' voltage Input leakage current Output leakage current Operating current Standby current
VOL VOH ILI ILO ICC1 ICC2 ICCL
IOL = 2.1 mA IOH = -1.0 mA VIN = 0 V to VCC CE = VIH, VI/O = 0 V to VCC Outputs open (OE = VCC) Outputs open (OE = VIH) CE VCC - 0.2 V All other input pins = 0 V to VCC VCC - 0.5 -1.0 -1.0 8 8
0.5 1.0 1.0 10 10 1.0
V V A A mA mA A 1 2
NOTES: 1. CE = 0 V; all other input pins = 0 V to VCC 2. CE = VIL; all other input pins = VIL to VIH
AC CHARACTERISTICS (VCC = 3 V 10%, TA = 0 to +50C) (1) READ CYCLE
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time Chip enable Low to output in Low-Z Output enable access time Output enable Low to output in Low-Z Chip disable to output in High-Z Output enable to output in High-Z Output hold time
tRC tAA tACE tCLZ tOE tOLZ tCHZ tOHZ tOH
1000 1000 1000 10 100 10 0 0 10 40 40
ns ns ns ns ns ns ns ns ns 1 1 1 1
NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
3
LH5116S
CMOS 16K (2K x 8) Static RAM
(2) WRITE CYCLE (VCC = 3 V 10%, TA = 0 to +50C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Write cycle time Chip enable to end of write Address valid time Address setup time Write pulse width Write recovery time WE Low to output in High-Z Data valid to end of write Data hold time Output active from end of write Output enable to output in High-Z
tWC tCW tAW tAS tWP tWR tWHZ tDW tDH tOW tOHZ
1000 100 100 0 100 20 30 50 20 10 0 40
ns ns ns ns ns ns ns ns ns ns ns 1 1 1
NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER MODE NOTE
Input voltage amplitude Input rise/fall time Timing reference level Output load conditions
0 to VCC 10 ns 1.5 V CL (100 pF) 1
NOTE: 1. Includes scope and jig capacitance.
DATA RETENTION CHARACTERISTICS (TA = 0 to +50C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Data retention voltage Data retention current Chip disable to data retention Recovery time
NOTES: 1. TA = 25C 2. t RC = Read cycle time
VCCDR ICCDR tCDR tR
CE VCCDR - 0.2 V CE VCCDR - 0.2 V, VCCDR = 2.0 V
2.0 1.0 0.2 0 tRC
V A ns ns 2 1
CAPACITANCE 1 (TA = 25C, f = 1MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input capacitance Input/output capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V
7 10
pF pF
NOTE: 1. This parameter is sampled and not production tested.
4
CMOS 16K (2K x 8) Static RAM
LH5116S
tCDR VCC 2.5 V 2.2 V VCCDR CE 0V
DATA RETENTION MODE
tR
CE VCCDR -0.2 V
5116S-6
Figure 3. Low Voltage Data Retention
tRC
A0 - A10 tAA tACE CE tOE OE tOLZ tCLZ DOUT NOTE: WE = "HIGH"
DATA VALID
tOH
tCHZ
tOHZ
5116S-3
Figure 4. Read Cycle
5
LH5116S
tWC A0 - A10 tAW tWR (NOTE 3)
CMOS 16K (2K x 8) Static RAM
tCW
CE tAS tWP (NOTE 2) WE tWHZ (NOTE 4) DOUT tDW tDH (NOTE 6) DIN NOTES: OE = 'LOW' tOW (NOTE 5)
1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input signals of opposite logic level must not be applied.
5116S-4
Figure 5. Write Cycle 1 (Note 1)
tWC A0 - A10 tAW tWR (NOTE 3) OE tCW CE tAS tWP (NOTE 2) WE tOHZ tOW tOLZ (NOTE 5)
DOUT (NOTE 4)
tDW tDH (NOTE 6)
DIN NOTES: 1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE and OE are LOW during this period, the input/output pins are in the output state. During this state, input signals of opposite logic level must not be applied.
5116S-5
Figure 6. Write Cycle 2 (Note 1) 6
CMOS 16K (2K x 8) Static RAM
LH5116S
PACKAGE DIAGRAM
24SOP (SOP024-P-0450B)
1.27 [0.050] TYP. 1.70 [0.067] 13 8.80 [0.346] 12.40 [0.488] 8.40 [0.331] 11.60 [0.457]
0.50 [0.120] 0.30 [0.012]
24
10.60 [0.417]
1 15.60 [0.614] 15.20 [0.598]
12 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
24SOP
24-pin, 450-mil SOP
ORDERING INFORMATION
LH5116S Device Type N Package
24-pin, 450-mil SOP (SOP024-P-0450B)
CMOS 16K (2K x 8) Static RAM
Example: LH5116SN (CMOS 16K (2K x 8) Static RAM, 450-mil SOP)
5116S-7
7

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